Vfrdtyky

I dont know how to deal with the third part of the priority encoder where if more than one 1 appear in the inputs the output will be the number of the most significant 1. At first i thought maybe making the for loop so the i decreases but i couldnt really apply it. And i am pretty sure there is an easier way than creating all the 4 bit combinations for the VD.

The truth table:
http://prntscr.com/limnd8
and examples of how it should work :

D3=0, D2=0, D1=0, D0=0 --> Υ1=0, Υ0=0, Zeros =1

D3=1, D2=1, D1=0, D0=1 --> Υ1=1, Υ0=1, Zeros =0

D3=0, D2=1, D1=0, D0=1 --> Υ1=1, Υ0=0, Zeros =0

module priorityenc_behav( D0, D1, D2, D3, Y0, Y1, Z);



input D0, D1, D2, D3;

output reg Y0, Y1, Z;

reg [3:0] VD;

integer i;





always @ (D0,D1,D2,D3)

 begin

    VD = 4'b0000;

    if ({D3,D2,D1,D0} == 4'b0000)

        {Y1,Y0,Z} = 3'b001;



    VD = 4'b1111;

    for (i=3; i>=0; i=i-1)

     begin

        if ((2**i) == {D3,D2,D1,D0})

         begin

            {Y1,Y0} = i;

            Z = 0;

         end

//////////////////////////

        else if(VD[ == {D3,D2,D1,D0})

         begin

            {Y1,Y0} = i;            

            Z = 0;

//////////////////////

         end

     end





 end

endmodule

I modified it very little bit but i cant control the else if statement correctly

module priorityenc_behav( D0, D1, D2, D3, Y0, Y1, Z);



input D0, D1, D2, D3;

output reg Y0, Y1, Z;

//reg [3:0] VD;

integer i;





always @ (D0,D1,D2,D3)

 begin



    if ({D3,D2,D1,D0} == 4'b0000)

        {Y1,Y0,Z} = 3'b001;



    for (i=3; i>=0; i=i-1)

     begin

        if ({D3,D2,D1,D0} == (2**i))

         begin

            {Y1,Y0} = i;

            Z = 0;

         end

        else if({D3,D2,D1,D0}>2**i)

             begin

                {Y1,Y0} = i;            

                Z = 0;

             end    

     end





 end

endmodule

Ok, I reverted my for back so i increases and it works i think . I will leave it a little more if someone want to see anything or he/she can make the code make less space but leaving the signals as they are(or if they add one reg like the commented one kinda)

Here is a variant based on your code which works. The idea is that you check using the first '1' in the Ds and stop checking after it. To check them you can use bitwise &.

module priorityenc_behav( D0, D1, D2, D3, Y0, Y1, Z);

   input D0, D1, D2, D3;

   output reg Y0, Y1, Z;



   integer    i;

   reg        flag;





  always @* begin

   if ({D3,D2,D1,D0} == 4'b0000)

    {Y1,Y0,Z} = 3'b001;

   else begin

     flag = 0;

     for (i=3; i>=0; i=i-1) begin

      if (flag == 0 && ({D3,D2,D1,D0} & (4'b0001 << i)) != 0) begin

       flag = 1;

       {Y1, Y0} = i;

       Z = 1'b0;

      end

     end

    end

   end



endmodule

The other version is much simpler and more readable in your case:

module priorityenc_behav( D0, D1, D2, D3, Y0, Y1, Z);



input D0, D1, D2, D3;

output reg Y0, Y1, Z;



always @* begin

 casez({D3,D2,D1,D0})

  4'b0000: {Y1,Y0,Z} = 3'b001; 

  4'b0001: {Y1,Y0,Z} = 3'b000;

  4'b001?: {Y1,Y0,Z} = 3'b010;

  4'b01??: {Y1,Y0,Z} = 3'b100;

  4'b1???: {Y1,Y0,Z} = 3'b110;

 endcase

end

endmodule