how system verilog program module avoids timing issues ?
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why exactly the program module concept came into picture ? I read in one book that it is to avoid the timing violations. How ?
Any suggestions or help is highly appreciated.
Thank You
Sam
system-verilog
asked Nov 17 '18 at 6:43
user226751user226751
1
add a comment |
why exactly the program module concept came into picture ? I read in one book that it is to avoid the timing violations. How ?
Any suggestions or help is highly appreciated.
Thank You
Sam
system-verilog
asked Nov 17 '18 at 6:43
user226751user226751
1
1
Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49
add a comment |
why exactly the program module concept came into picture ? I read in one book that it is to avoid the timing violations. How ?
Any suggestions or help is highly appreciated.
Thank You
Sam
system-verilog
asked Nov 17 '18 at 6:43
user226751user226751
1
why exactly the program module concept came into picture ? I read in one book that it is to avoid the timing violations. How ?
Any suggestions or help is highly appreciated.
Thank You
Sam
system-verilog
system-verilog
asked Nov 17 '18 at 6:43
user226751user226751
1
asked Nov 17 '18 at 6:43
user226751user226751
1
asked Nov 17 '18 at 6:43
user226751user226751
1
asked Nov 17 '18 at 6:43
user226751user226751
1
asked Nov 17 '18 at 6:43
user226751user226751
1
1
1
Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49
add a comment |
1
Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49
1
1
Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49
add a comment |
1 Answer
1
active
oldest
votes
Normally, a question like this is considered to broad and opinionated for SO. But since I was directly involved in the development and standardization of SystemVerilog, I can present a few facts from an article I wrote about it.
Program blocks came directly from a donation of the Vera language to SystemVerilog by Synopsys , and try to mimic the scheduling semantics that a PLI application has interacting with a Verilog simulator.
A program block's original purpose in SystemVerilog was to avoid race conditions (not timing violations) between sampling and driving signals between the DUT and the Testbench. It also controlled starting and termination of the "test".
Since its introduction, a number of other features within SystemVerilog have subsumed the need for program blocks as I explain in my article.
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
add a comment |
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Normally, a question like this is considered to broad and opinionated for SO. But since I was directly involved in the development and standardization of SystemVerilog, I can present a few facts from an article I wrote about it.
Program blocks came directly from a donation of the Vera language to SystemVerilog by Synopsys , and try to mimic the scheduling semantics that a PLI application has interacting with a Verilog simulator.
A program block's original purpose in SystemVerilog was to avoid race conditions (not timing violations) between sampling and driving signals between the DUT and the Testbench. It also controlled starting and termination of the "test".
Since its introduction, a number of other features within SystemVerilog have subsumed the need for program blocks as I explain in my article.
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
add a comment |
Normally, a question like this is considered to broad and opinionated for SO. But since I was directly involved in the development and standardization of SystemVerilog, I can present a few facts from an article I wrote about it.
Program blocks came directly from a donation of the Vera language to SystemVerilog by Synopsys , and try to mimic the scheduling semantics that a PLI application has interacting with a Verilog simulator.
A program block's original purpose in SystemVerilog was to avoid race conditions (not timing violations) between sampling and driving signals between the DUT and the Testbench. It also controlled starting and termination of the "test".
Since its introduction, a number of other features within SystemVerilog have subsumed the need for program blocks as I explain in my article.
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
add a comment |
Normally, a question like this is considered to broad and opinionated for SO. But since I was directly involved in the development and standardization of SystemVerilog, I can present a few facts from an article I wrote about it.
Program blocks came directly from a donation of the Vera language to SystemVerilog by Synopsys , and try to mimic the scheduling semantics that a PLI application has interacting with a Verilog simulator.
A program block's original purpose in SystemVerilog was to avoid race conditions (not timing violations) between sampling and driving signals between the DUT and the Testbench. It also controlled starting and termination of the "test".
Since its introduction, a number of other features within SystemVerilog have subsumed the need for program blocks as I explain in my article.
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
Normally, a question like this is considered to broad and opinionated for SO. But since I was directly involved in the development and standardization of SystemVerilog, I can present a few facts from an article I wrote about it.
Program blocks came directly from a donation of the Vera language to SystemVerilog by Synopsys , and try to mimic the scheduling semantics that a PLI application has interacting with a Verilog simulator.
A program block's original purpose in SystemVerilog was to avoid race conditions (not timing violations) between sampling and driving signals between the DUT and the Testbench. It also controlled starting and termination of the "test".
Since its introduction, a number of other features within SystemVerilog have subsumed the need for program blocks as I explain in my article.
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
answered Nov 17 '18 at 16:29
dave_59dave_59
21.1k21639
21.1k21639
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Please Take the Tour , and be sure to read How do I ask a good question? . try to give a detailed information about your question. What issue your facing? , where your blocking? , what you tried so far? like the way you have to give.
– Agilanbu
Nov 17 '18 at 6:50
timing issues have nothing to do with modules.
– Serge
Nov 17 '18 at 14:49